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Core/CommandProcessor: Reformat single/dual core dependent MMIO handlers.

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Admiral H. Curtiss 2022-11-23 21:58:18 +01:00
parent 0a6fdb9c13
commit 545fee9c94
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GPG key ID: F051B4C4044F33FB
1 changed files with 88 additions and 65 deletions
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71
Source/Core/VideoCommon/CommandProcessor.cpp
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@ -265,9 +265,11 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>()); mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
// Some MMIOs have different handlers for single core vs. dual core mode. // Some MMIOs have different handlers for single core vs. dual core mode.
mmio->Register( const bool is_on_thread = IsOnThread();
base | FIFO_RW_DISTANCE_LO, MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_lo_r;
IsOnThread() ? MMIO::ComplexRead<u16>([](Core::System&, u32) { if (is_on_thread)
{
fifo_rw_distance_lo_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >= if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
{ {
@ -281,13 +283,20 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
fifo.CPWritePointer.load(std::memory_order_relaxed) - fifo.CPWritePointer.load(std::memory_order_relaxed) -
fifo.CPBase.load(std::memory_order_relaxed) + 32); fifo.CPBase.load(std::memory_order_relaxed) + 32);
} }
}) : });
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)), }
else
{
fifo_rw_distance_lo_r = MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance));
}
mmio->Register(base | FIFO_RW_DISTANCE_LO, fifo_rw_distance_lo_r,
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance), MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
WMASK_LO_ALIGN_32BIT)); WMASK_LO_ALIGN_32BIT));
mmio->Register(base | FIFO_RW_DISTANCE_HI,
IsOnThread() ? MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_hi_r;
MMIO::ComplexRead<u16>([](Core::System&, u32) { if (is_on_thread)
{
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >= if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
@ -304,41 +313,55 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
fifo.CPBase.load(std::memory_order_relaxed) + 32) >> fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
16; 16;
} }
}) : });
MMIO::ComplexRead<u16>([](Core::System&, u32) { }
else
{
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16; return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
}), });
}
mmio->Register(base | FIFO_RW_DISTANCE_HI, fifo_rw_distance_hi_r,
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) { MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT); WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
Fifo::RunGpu(); Fifo::RunGpu();
})); }));
mmio->Register( mmio->Register(
base | FIFO_READ_POINTER_LO, base | FIFO_READ_POINTER_LO,
IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) : is_on_thread ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)), MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT)); MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
mmio->Register(
base | FIFO_READ_POINTER_HI, MMIO::ReadHandlingMethod<u16>* fifo_read_hi_r;
IsOnThread() ? MMIO::ComplexRead<u16>([](Core::System&, u32) { MMIO::WriteHandlingMethod<u16>* fifo_read_hi_w;
if (is_on_thread)
{
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16; return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
}) : });
MMIO::ComplexRead<u16>([](Core::System&, u32) { fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
}),
IsOnThread() ? MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT); WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed), fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
std::memory_order_relaxed); std::memory_order_relaxed);
}) : });
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) { }
else
{
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
Fifo::SyncGPUForRegisterAccess();
return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
});
fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
Fifo::SyncGPUForRegisterAccess(); Fifo::SyncGPUForRegisterAccess();
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT); WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
})); });
}
mmio->Register(base | FIFO_READ_POINTER_HI, fifo_read_hi_r, fifo_read_hi_w);
} }
void GatherPipeBursted() void GatherPipeBursted()